Securing netlist-level FPGA design through exploiting process variation and degradation
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
| Hi-index | 0.00 |
This paper presents a method of knowledge representation for very large scale integration (VLSI) chip design which provides the necessary information for abstraction from the physical design to gate-level logic through a high-level behavioral model. The representation scheme used by the ANTISTROFEAS system utilizes a hierarchical attributed graph structure which consists of incrementally abstracted design information for the VLSI system. This method of knowledge representation is well-suited to reverse-engineering of VLSI chips from the layer mask layout data, but is also applicable to applications at many levels of the design process including design rule checking, logic synthesis, design verification, and partitioning-compaction problems. The representation scheme is applicable to any VLSI technology, and is designed to take advantage of artificial intelligence. expert system techniques, by disassociating the representation and manipulation of the VLSI design data from the rules which govern its correctness and transformation for other usage.