On using adversary simulators to obtain tight lower bounds for response times

Authors:
Rômulo Silva de Oliveira;Andreu Carminati;Renan Augusto Starke
Affiliations:
Univ. Fed. de Santa Catarina DAS-CTC-UFSC, Florianópolis-SC, Brazil;Univ. Fed. de Santa Catarina DAS-CTC-UFSC, Florianópolis-SC, Brazil;Univ. Fed. de Santa Catarina DAS-CTC-UFSC, Florianópolis-SC, Brazil
Venue:
Proceedings of the 27th Annual ACM Symposium on Applied Computing
Year:
2012

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Abstract

Many embedded systems have soft real-time constraints and it is useful to have an estimate for the worst-case response time of each task. Formal analysis provides safe upper bounds but they are too pessimistic for complex architectures. Simulators can be used to establish a lower bound for the worst-case response time, but classic simulators apply arrival patterns originally conceived for uniprocessor and fail to achieve a good estimate. In this paper we present the concept of an adversary simulator that generates arrival patterns to stress the system. We implemented a simple and fast heuristic that allows the adversary simulator to obtain lower bounds that are considerably tighter than those of classic simulators. We designed the heuristic specifically for fixed-priority scheduling with Deadline Monotonic and Deadline minus Computation Time Monotonic priority ordering.