Algorithms for Scheduling Imprecise Computations
Computer - Special issue on real-time systems
Modern heuristic techniques for combinatorial problems
Modern heuristic techniques for combinatorial problems
Holistic schedulability analysis for distributed hard real-time systems
Microprocessing and Microprogramming - Parallel processing in embedded real-time systems
Preemptive Multiprocessor Scheduling Anomalies
IPDPS '02 Proceedings of the 16th International Symposium on Parallel and Distributed Processing
RTAS '04 Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium
Measuring the Performance of Schedulability Tests
Real-Time Systems
Response-Time Analysis for Globally Scheduled Symmetric Multiprocessor Platforms
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
A simulation methodology for worst-case response time estimation of distributed real-time systems
Proceedings of the conference on Design, automation and test in Europe
Schedulability Analysis of Global Scheduling Algorithms on Multiprocessor Platforms
IEEE Transactions on Parallel and Distributed Systems
New Response Time Bounds for Fixed Priority Multiprocessor Scheduling
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Brute-force determination of multiprocessor schedulability for sets of sporadic hard-deadline tasks
OPODIS'07 Proceedings of the 11th international conference on Principles of distributed systems
Journal of Systems and Software
RTAS '11 Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
On using adversary simulators to obtain tight lower bounds for response times
Proceedings of the 27th Annual ACM Symposium on Applied Computing
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There are many real-time systems where it is useful to have an estimate for the worst-case response time of each task. Simulators can be used to establish a lower bound on the worst-case response time. But classic simulators apply arrival patterns originally conceived for uniprocessor and fail to achieve a good estimate for the worst-case response time when multiprocessors are used. An adversary simulator generates arrival patterns to stress the processing capacity of the system and, in this way, to obtain tighter estimates. In this paper we present a new heuristic for adversary simulators specifically designed for fixed-priority zero-laxity (FPZL) scheduling. This new adversary algorithm is simple and fast, and it works with both deadline monotonic (DMPO) and deadline minus computation monotonic (DCMPO) priority assignment policies. The evaluation shows that the adversary simulator proposed in this paper is more effective when FPZL scheduling is used. We also compare four scheduling approaches (FP-DMPO, FP-DCMPO, FPZL-DMPO and FPZL-DCMPO) using an appropriate adversary simulator for each one.