A process algebra interpretation of a verification oriented overlanguage of VHDL

Authors:
Catherine Bayol;Bernard Soulas;Dominique Borrione;Fulvio Corno;Paolo Prinetto
Affiliations:
EDF/DER, 77250 Moret/Loing, France;EDF/DER, 77250 Moret/Loing, France;J. Fourier University, IMAG/ARTEMIS Lab, Grenoble, France;Politecnico di Torino, Dpt Automatica e Informatica, Turin, Italy;Politecnico di Torino, Dpt Automatica e Informatica, Turin, Italy
Venue:
EURO-DAC '94 Proceedings of the conference on European design automation
Year:
1994

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Abstract