Symbolic model checking: 1020 states and beyond
Information and Computation - Special issue: Selections from 1990 IEEE symposium on logic in computer science
Theoretical Computer Science
Symbolic model checking for real-time systems
Information and Computation
IEEE Spectrum
TACAs '96 Proceedings of the Second International Workshop on Tools and Algorithms for Construction and Analysis of Systems
Comparing Timed C/E Systems with Timed Automata (Abstract)
HART '97 Proceedings of the International Workshop on Hybrid and Real-Time Systems
Computers and Electronics in Agriculture
Formal verification of PLC controlled systems using sensor graphs
CASE'09 Proceedings of the fifth annual IEEE international conference on Automation science and engineering
Reachability analysis of a switched buffer network
HSCC'07 Proceedings of the 10th international conference on Hybrid systems: computation and control
Finite abstractions for hybrid systems with stable continuous dynamics
Discrete Event Dynamic Systems
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An approach to the formal verification of logic controllers for processes with switched continuous dynamics is presented. The method builds on modular, timed discrete event models of the plant and the controller. Subsystems with continuous dynamics are approximated algorithmically. The formal verification consists of determining the reachable discrete states of the resulting model and comparing it to a set of undesired states. For this purpose, the tool HyTech is applied. The approach is illustrated by the treatment of a process engineering example.