DCT-Domain Embedded Memory Compression for Hybrid Video Coders
Journal of VLSI Signal Processing Systems - Special issue on recent advances in the design and implementation of signal processing systems
Low-Complexity Scalable Image Compression
DCC '00 Proceedings of the Conference on Data Compression
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This paper presents an efficient DCT-based embedded image coder designed for I(intra)-frame coding in a very low bit rate video codec. Motivated by the recognition that a DCT (discrete cosine transform) on N×N blocks of an image can be viewed as a wavelet decomposition with a uniform N×N-subband decomposition, the proposed coder rearranges the DCT transformed image into a 2-level wavelet pyramid structure and makes use of improved embedded zerotree coding. The proposed rearrangement structure is quite well coupled with a embedded zerotree coding. The resulting DCT-based embedded image coder shows a better rate-distortion performance than conventional H.263 and MPEG4 as well as EZW-style coders. Also, the performance of the proposed new coder is comparable to that of state-of-art still image compression methods. In addition, the embedded feature of the proposed coder makes it possible to encode the I-frame at the exactly chosen bit rate