A new CFA interpolation framework
Signal Processing
VLSI Implementation of low-power high-quality color interpolation processor for CCD camera
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Compression of Bayer-pattern video sequences using adjusted chroma subsampling
IEEE Transactions on Circuits and Systems for Video Technology
Directonal weighting-based demosaicking algorithm
PCM'04 Proceedings of the 5th Pacific Rim Conference on Advances in Multimedia Information Processing - Volume Part II
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This paper presents an interpolation method for digital still cameras (DSCs) which is based on color signal correlation. The authors have developed a method of reducing aliasing by increasing the resolution of color signals in DSCs that use a single-plate charge coupled device (CCD) with a primary color filter array. The new method interpolates signals by taking advantage of the fact that color signal variations are similar to one another in a local region of an image. It selects the signal that shows the higher correlation, either in the horizontal or vertical directions, at color signal positions subject to interpolation, thus improving the color resolution. First, the effectiveness of the new method was verified using image simulation. Next, the prototype hardware was fabricated. The prototype is fitted with an original reduced instruction set computer (RISC) built-in dynamic random access memory (DRAM) for processing image signals to provide high-speed camera signal processing. The authors also confirmed that the effectiveness of the new method was also established in actual products