Combining labeled and unlabeled data with co-training
COLT' 98 Proceedings of the eleventh annual conference on Computational learning theory
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Measuring Benchmark Similarity Using Inherent Program Characteristics
IEEE Transactions on Computers
Efficiently exploring architectural design spaces via predictive modeling
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Using Machine Learning to Guide Architecture Simulation
The Journal of Machine Learning Research
Analyzing Co-training Style Algorithms
ECML '07 Proceedings of the 18th European conference on Machine Learning
NeC4.5: Neural Ensemble Based C4.5
IEEE Transactions on Knowledge and Data Engineering
CPR: Composable performance regression for scalable multiprocessor models
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A hybrid generative/discriminative approach to semi-supervised classifier design
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 2
Unsupervised and semi-supervised multi-class support vector machines
AAAI'05 Proceedings of the 20th national conference on Artificial intelligence - Volume 2
Semi-supervised regression with co-training
IJCAI'05 Proceedings of the 19th international joint conference on Artificial intelligence
Chip Multiprocessor Design Space Exploration through Statistical Simulation
IEEE Transactions on Computers
Semi-supervised learning by disagreement
Knowledge and Information Systems
Unlabeled data and multiple views
PSL'11 Proceedings of the First IAPR TC3 conference on Partially Supervised Learning
Microarchitectural design space exploration made fast
Microprocessors & Microsystems
ACM Transactions on Intelligent Systems and Technology (TIST) - Special Section on Intelligent Mobile Knowledge Discovery and Management Systems and Special Issue on Social Web Mining
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During the design of a microprocessor, Design Space Exploration (DSE) is a critical step which determines the appropriate design configuration of the microprocessor. In the computer architecture community, supervised learning techniques have been applied to DSE to build models for predicting the qualities of design configurations. For supervised learning, however, considerable simulation costs are required for attaining the labeled design configurations. Given limited resources, it is difficult to achieve high accuracy. In this paper, inspired by recent advances in semi-supervised learning, we propose the COMT approach which can exploit unlabeled design configurations to improve the models. In addition to an improved predictive accuracy, COMT is able to guide the design of microprocessors, owing to the use of comprehensible model trees. Empirical study demonstrates that COMT significantly outperforms state-of-the-art DSE technique through reducing mean squared error by 30% to 84%, and thus, promising architectures can be attained more efficiently.