Analytical models for replicate-at-send multicasting in shared-memory switches
Performance Evaluation
Two-level cache architecture to reduce memory accesses for IP lookups
Proceedings of the 23rd International Teletraffic Congress
Input queued switches for variable length packets: analysis for Poisson and self-similar traffic
Computer Communications
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This article proposes a scalable multi-QoS IP+ATM switch router architecture. The proposed switch router is based on a core ATM switching system with multi-QoS capability. Forwarding engines and a routing engine are attached in front of the line cards of the ATM switching system. The FEs and RE are interconnected with each other via internal VCs. A novel longest matching algorithm is employed at the FE to achieve packet forwarding at wire-speed of OC-12c rate (622.08 Mb/s). Wire-speed unicast and multicast packet forwarding are performed using point-to-point and point-to-multipoint VCs in a unified way. Because FEs and RE are decoupled from the base ATM switching system, the full spectrum of ATM QoS capability is nicely applied for IP QoS control with a packet classification at the edge of the network. The core switching fabric is scalable from 40 to 160 Gb/s capacity (371 MPPS in terms of packet forwarding throughput). Feedback rate control is employed at each line card to eliminate congestion in the high-speed core switching fabric even with a small amount of buffer.