Parametric fault simulation and test vector generation
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Design and modeling of optimum quality spiral inductors with regularization and debye approximation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Adequate analytical device models for circuit simulators are required in the design of IC's, especially in analog design, because the reliability of simulation results is closely related to model accuracy. A semiempirical approach to device modeling offers many advantages over physics-based modeling, in which complex equations have to be solved, and seems to be the most appropriate for circuit simulation. However as this approach is not founded on a rigorous mathematical theory no general methodologies are available for its implementation. Furthermore, device models currently used in circuit simulators are derived by neglecting randomness in experimental data. This assumption is not realistic for mass-produced IC's where technological tolerances cause variations in the measured data, even if they are obtained using the same experimental conditions. The aim of this work is to develop a new scheme for semiempirical device modeling founded on the rigorous mathematical framework of “regularization theory” and to suggest a parameter extraction method based on Bayesian parameter estimation, which takes into account randomness in data. The application of the method to the development of an accurate model for MOS transistors shows the validity of the proposed theoretical approach which is further confirmed by extensive analysis of experimental data