Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A dedicated reconfigurable architecture for finite state machines
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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The N-input multiplexers based on CMOS switches are conventionally designed with the binary-tree structure to simplify the address decoder and obtain a reasonable delay, which estimates the propagation time from data input end to the output end of the multiplexers. However, this design strategy in general takes too much hardware and incurs too much delay. To reduce both delay and cost, some structures other than the binary-tree structure have to be used. Therefore, in this paper we propose a general procedure based on the heterogeneous-tree structure for designing fast large fan-in CMOS multiplexers. The results show that not only can the speed be increased but the cost can also be reduced considerably for the proposed circuits with various input sizes. In addition, we show that both the binary-tree structure and the uniform structure are special cases of the proposed approach