Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Symbolic analysis of analog circuits containing voltage mirrors and current mirrors
Analog Integrated Circuits and Signal Processing
Generalized multi-domain symbolic simplification
IMCAS'11 Proceedings of the 10th WSEAS international conference on Instrumentation, measurement, circuits and systems
Symbolic simplification by means of graph transformations
CSS'11 Proceedings of the 5th WSEAS international conference on Circuits, systems and signals
Worst-case control mechanism for approximate symbolic analysis
MMES'11/DEEE'11/COMATIA'11 Proceedings of the 2nd international conference on Mathematical Models for Engineering Science, and proceedings of the 2nd international conference on Development, Energy, Environment, Economics, and proceedings of the 2nd international conference on Communication and Management in Technological Innovation and Academic Globalization
Approximate symbolic analysis with emphasis on frequency filters
IMMURO'12 Proceedings of the 11th WSEAS international conference on Instrumentation, Measurement, Circuits and Systems, and Proceedings of the 12th WSEAS international conference on Robotics, Control and Manufacturing Technology, and Proceedings of the 12th WSEAS international conference on Multimedia Systems & Signal Processing
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Presents a circuit simplification method for the symbolic analysis of a linear or linearized (small-signal) analog circuit. Its goal is to generate simplified signal flow graphs describing the circuit's behavior in well-defined frequency intervals. These frequency subranges are automatically constructed based on numerical calculation of the system's poles and zeroes. The circuit reduction has been implemented using graph manipulation techniques. The order in which these manipulations are applied is based on a tradeoff between the error and the level of simplification they introduce. The technique can be used to symbolically localize poles and zeroes and inspect their observability. This allows generating symbolic expressions for poles and zeroes, which in optimal conditions lead to simple, interpretable expressions. The technique can also be used as preprocessor to simplify a circuit before analyzing it with standard approximate symbolic analysis techniques. In that case, it helps overcoming the time and memory constraints related to those techniques. Experimental results show the effectiveness of the approach