On-chip interconnect modeling by wire duplication

Authors:
Guoan Zhong;Cheng-Kok Koh;K. Roy
Affiliations:
Electr. & Comput. Eng. Dept., Purdue Univ., West Lafayette, IN, USA;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

Citing 0
Cited 2

Stable and compact inductance modeling of 3-D interconnect structures

Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A fast band-matching technique for interconnect inductance modeling

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Quantified Score

Hi-index	0.03

Visualization

Abstract

The authors present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L-1 matrix, where L is the inductance matrix, and constructs a sparse and stable equivalent circuit by windowing the original inductance matrix. The resulting circuit model is sparse and exhibits the same stability property as the K method. Numerical results show that the proposed wire duplication model has high accuracy and is more efficient than many existing techniques.