The effect of process variation on device temperature in FinFET circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
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This paper models and analyzes subthreshold and gate leakage currents in different double-gate (DG) devices, namely, a doped body symmetric device with polysilicon gates, an intrinsic body symmetric device with metal gates, and an intrinsic body asymmetric device with different front and back gate materials. The effect of variations in device parameters on the leakage components is also analyzed. Using the developed models, digital circuits (logic gates and static random access memory cells) designed with different DG structures are also analyzed. The analysis shows that the use of (near mid-gap) metal gate and intrinsic body devices significantly reduces both the total leakage and its sensitivity to parametric variations in DG devices and circuits