Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Efficient incremental analysis of on-chip power grid via sparse approximation
Proceedings of the 48th Design Automation Conference
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A statistical sampling-based parametric analysis is presented for analyzing large power grids in a "localized" fashion. By combining random walks with the notion of "importance sampling," the proposed technique is capable of efficiently computing the impacts of multiple circuit parameters on selected network nodes. A "new localized" sensitivity analysis is first proposed to solve not only the nominal node response but also its sensitivities with respect to multiple parameters using a single run of the random walks algorithm. This sampling-based technique is further extended from the first-order sensitivity analysis to a more general second-order analysis. By exploiting the natural spatial locality inherent in the proposed algorithm formulation, the second-order analysis can be performed efficiently even for a large number of global and local variation sources. The theoretical convergence properties of three importance sampling estimators for power grid analysis are presented, and their effectiveness is compared experimentally on several examples. The superior performance of the proposed technique is demonstrated by analyzing several large power grids under process and current loading variations to which the application of the existing brute-force simulation techniques becomes completely infeasible