Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model

• Authors: Mahilchi Milir Vaseekar Kumar;Spyros Tragoudas;Sreejit Chakravarty;Rathish Jayabharathi
• Venue: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• Year: 2006

A novel function-based method for error propagation is proposed for exact delay fault coverage, using a single rated clock for fault activation under any delay fault model. Sequential circuits without full scan are considered. A latched error at a flip-flop represents one or more delay faults and is allowed to propagate to an observable point with or without the support of other latched errors. Existing methods allow only one flip-flop to have an error during the propagation phase to simplify the process of error propagation at the expense of decreased fault coverage. The advantage of the proposed method is demonstrated experimentally using the path-delay-fault model with more than 20% improvement in fault coverage