Hierarchical Verification of Galois Field Circuits

Authors:
D. Mukhopadhyay;G. Sengar;D. R. Chowdhury
Affiliations:
Indian Inst. of Technol., Madras;-;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2007

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Abstract

This paper proposes a hierarchical method for the formal hardware verification of Galois field architecture circuits. The reduced ordered functional decision diagram has been explored. The proposed method has been found to lead to significant gains in time and space, depending on the resources that are available. The theoretical claims that were made have been supported by experiments.