VLSI floorplan generation and area optimization using AND-OR graph search
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
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Given a sliceable floorplan and cell sizes, Otten and Stockmeyer [1983] presented an algorithm to find an optimal implementation for each cell. The authors consider a generalized optimal sizing problem on a set of slicing trees related to an adjacency graph. For computation efficiency, they combine the tree enumeration and sizing procedures in a unified algorithm where floorplan trees and sizes are computed simultaneously. The tree enumeration is based on adjacency graph of the input cells, which ensures that the adjacency requirements of the cells are preserved. Time complexity of the algorithm is analyzed and experimental results using MCNC benchmarks are reported