Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications

  • Authors:
  • Stijn Eyerman;Kristof Du Bois;Lieven Eeckhout

  • Affiliations:
  • ELIS Department, Ghent University, Belgium;ELIS Department, Ghent University, Belgium;ELIS Department, Ghent University, Belgium

  • Venue:
  • ISPASS '12 Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software
  • Year:
  • 2012

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Abstract

Multi-threaded workloads typically show sublinear speedup on multi-core hardware, i.e., the achieved speedup is not proportional to the number of cores and threads. Sublinear scaling may have multiple causes, such as poorly scalable synchronization leading to spinning and/or yielding, and interference in shared resources such as the last-level cache (LLC) as well as the main memory subsystem. It is vital for programmers and processor designers to understand scaling bottlenecks in existing and emerging workloads in order to optimize application performance and design future hardware. In this paper, we propose the speedup stack, which quantifies the impact of the various scaling delimiters on multi-threaded application speedup in a single stack. We describe a mechanism for computing speedup stacks on a multi-core processor, and we find speedup stacks to be accurate within 5.1% on average for sixteen-threaded applications. We present several use cases: we discuss how speedup stacks can be used to identify scaling bottlenecks, classify benchmarks, optimize performance, and understand LLC performance.