Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap

Authors:
Gabriel Loh;Mark D. Hill
Affiliations:
Advanced Micro Devices;University of Wisconsin—Madison
Venue:
IEEE Micro
Year:
2012

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Abstract

This work efficiently enables conventional block sizes for very large die-stacked DRAM caches with two innovations: it makes hits faster with compound-access scheduling and misses faster with a MissMap. The combination of these mechanisms enables the new organization to deliver performance comparable to that of an idealistic DRAM cache that employs an impractically large SRAM-based on-chip tag array.