Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache

Authors:
Fazal Hameed;Lars Bauer;Jörg Henkel
Affiliations:
Karlsruhe Institute of Technology (KIT), Germany;Karlsruhe Institute of Technology (KIT), Germany;Karlsruhe Institute of Technology (KIT), Germany
Venue:
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Year:
2013

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Abstract

On-chip DRAM cache has the advantage of increased cache capacity that may alleviate the memory bandwidth problem. Recent research has demonstrated the benefits of high capacity on-chip DRAM cache that leads to reduced off-chip accesses. However, state-of-the-art has not taken into consideration the cache access patterns of concurrently running heterogeneous applications that can cause inter-core cache contention. We therefore propose an adaptive bank mapping policy in response to the diverse requirements of applications with different cache access behaviors that -- as a result -- reduces inter-core cache contention in DRAM-based cache architectures. On average, our adaptive bank mapping policy increases the harmonic mean instruction-per-cycle throughput by 19.3% (max. 71%) compared to state-of-the-art bank mapping policies.