Cost-effective video filtering solution for real-time vision systems
EURASIP Journal on Applied Signal Processing
IEEE Transactions on Neural Networks
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Based on the previously developed sorting networks, a new VLSI architecture suitable for two-dimensional (2-D) rank-order filtering is proposed. The major advantage of the proposed architecture is their fast response time, modular architecture, and simple and regular interconnection. Generally speaking, the throughput of the proposed architecture is (N-1) times faster than using a one-dimensional rank-order filter for 2-D N×N data. The concept of block processing is also incorporated into the design to reduce the time-area complexity of the proposed architecture. Roughly speaking, the complexity is reduced to 2/3 and 1/2 compared with a rank-order and median filter without using a block processing architecture, respectively. A 3×3 median filter with block processing architecture is implemented through a 0.8 μm single-poly double-metal CMOS process. The results are correct with a clock rate up to 125 MHz