Survey of Stochastic Computing
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Stochastic circuits for real-time image-processing applications
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 35.68 |
A new stochastic decoding algorithm, called Delayed Stochastic (DS) decoding, is introduced to implement low-density-parity-check (LDPC) decoders. The delayed stochastic decoding uses an alternative method to track probability values, which results in reduction of hardware complexity and memory requirement of the stochastic decoders. It is therefore suitable for fully-parallel implementation of long LDPC codes with applications in optical communications. Two decoders are implemented using the DS algorithm for medium (2048, 1723) and long (32768, 26624) LDPC codes. The decoders occupy 3.93- ${\hbox{mm}}^{2}$ and 56.5- ${\hbox{mm}}^{2}$ silicon area using 90-nm CMOS technology and provide maximum core throughputs of 172.4 and 477.7 Gb/s at ${E_{b}\over N_{o}}={\hbox{5.5}}$ and 4.8 dB, respectively.