A High Speed VLSI Architecture for Handwriting Recognition
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
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A 64x64 pixel vision sensor performs adaptive background subtraction and event detection at very low power consumption. The chip is based on a VLSI-oriented vision algorithm, implemented at pixel-level, mimicking the basic process of pre-attentive visual perception. Anomalous pixel behaviors are detected and coded into a 2-bit/pixel. Each pixel integrates two programmable Switched-Capacitors Low-Pass Filters and two clocked comparators, which are fundamental blocks for the execution of the vision algorithm. The 45T square pixel has a pitch of 26μm and a fill factor of 12%. The vision sensor consumes 33μW at 13 fps and 3.3V. This turns into a computing performance of 42 GOPS/W and 4 GOPS/mm2, which are values aligned with the most advanced computational vision sensors.