Off-Line Cursive Script Word Recognition
IEEE Transactions on Pattern Analysis and Machine Intelligence
Efficient Image Processing Algorithms on the Scan Line Array Processor
IEEE Transactions on Pattern Analysis and Machine Intelligence
The evolution of the PAPRICA system
Integrated Computer-Aided Engineering
Design and Implementation of the PAPRICA Parallel Architecture
Journal of VLSI Signal Processing Systems
High-speed recognition of handwritten amounts on Italian checks
Knowledge-based intelligent techniques in character recognition
Neural Networks: A Comprehensive Foundation
Neural Networks: A Comprehensive Foundation
Implementation of a SliM Array Processor
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
Recognition-Based Segmentation of On-Line Hand-Printed Words
Advances in Neural Information Processing Systems 5, [NIPS Conference]
A Linear Array Parallel Image Processor: SliM-II
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Image Analysis and Mathematical Morphology
Image Analysis and Mathematical Morphology
Unification of neural and wavelet networks and fuzzy systems
IEEE Transactions on Neural Networks
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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This article presents PAPRICA-3, a VLSI-oriented architecture for real-time processing of images and its implementation on HACRE, a high-speed, cascadable, 32-processors VLSI slice. The architecture is based on an array of programmable processing elements with the instruction set tailored to image processing, mathematical morphology, and neural networks emulation. Dedicated hardware features allow simultaneous image acquisition, processing, neural network emulation, and a straightforward interface with a hosting PC.HACRE has been fabricated and successfully tested at a clock frequency of 50 MHz. A board hosting up to four chips and providing a 33 MHz PCI interface has been manufactured and used to build BEATR IX, a system for the recognition of handwritten check amounts, by integrating image processing and neural network algorithms (on the board) with context analysis techniques (on the hosting PC).