Image Analysis Using Mathematical Morphology
IEEE Transactions on Pattern Analysis and Machine Intelligence
A prototype pyramid machine for hierarchical cellular logic
Parallel computer vision
IEEE Transactions on Pattern Analysis and Machine Intelligence - Special Issue on Industrial Machine Vision and Computer Vision Technology:8MPart
The Abingdon Cross Benchmark Survey
Computer
Pyramidal architectures for computer vision
Pyramidal architectures for computer vision
Processor Arrays: Architecture and Applications
Processor Arrays: Architecture and Applications
Word parallelism vs spatial parallelism: a performance optimization technique on the PAPRICA system
PDP '95 Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing
Using a massively parallel architecture for integrated circuits testing
PDP '95 Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing
Image Analysis and Mathematical Morphology
Image Analysis and Mathematical Morphology
Vision-based road detection in automotive systems: a real-time expectation-driven approach
Journal of Artificial Intelligence Research
GOLD: a parallel real-time stereo vision system for generic obstacle and lane detection
IEEE Transactions on Image Processing
A High Speed VLSI Architecture for Handwriting Recognition
Journal of VLSI Signal Processing Systems - Parallel VLSI architectures for image and video processing
Computer
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In this paper PAPRICA, a massively parallel coprocessor devoted tothe analysis of bitmapped images is presented considering first thecomputational model, then the architecture and its implementation, andfinally the performance analysis. The main goal of the project was todevelop a subsystem to be attached to a standard workstation and to operateas a specialized processing module in dedicated systems. The computationalmodel is strongly related to the concepts of mathematical morphology, andtherefore the instruction set of the processing units implements basicmorphological transformations. Moreover, the specific processorvirtualization mechanism allows to handle and process multiresolution datasets. The actual implementation consists of a mesh of 256 single bitprocessing units operating in a SIMD style and is based on a set of customVLSI circuits. The architecture comprises specific hardware extensions thatsignificantly improved performances in real-time applications.