Optimization of SEU Simulations for SRAM Cells Reliability under Radiation

  • Authors:
  • K. Castellani-Coulié;H. Aziza;G. Micolau;J-M. Portal

  • Affiliations:
  • IM2NP-UMR CNRS 6242/Université Aix-Marseille, IMT Technopôle de Château--Gombert, Marseille Cedex 20, France 13451;IM2NP-UMR CNRS 6242/Université Aix-Marseille, IMT Technopôle de Château--Gombert, Marseille Cedex 20, France 13451;IM2NP-UMR CNRS 6242/Université Aix-Marseille, IMT Technopôle de Château--Gombert, Marseille Cedex 20, France 13451;IM2NP-UMR CNRS 6242/Université Aix-Marseille, IMT Technopôle de Château--Gombert, Marseille Cedex 20, France 13451

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 2012

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Abstract

A simplified RC circuit is used to simulate effects of ionizing particles in a 90 nm SRAM. The main characteristics of the memory cell bit flip are discussed and a SEU criterion is presented. The effect of the surrounded circuit on the struck transistor is also discussed in order to extract parameters characteristic of the SEU occurrence.