Analysis and design of the true piecewise approximation logarithmic amplifiers

  • Authors:

  • M. Shaterian;A. Abrishamifar;H. Shamsi

  • Affiliations:

  • Electrical Engineering Faculty, Iran University of Science and Technology, Tehran, Iran;Electrical Engineering Faculty, Iran University of Science and Technology, Tehran, Iran;Electrical Engineering Faculty, K. N. Toosi University of Technology, Tehran, Iran

  • Venue:
  • Analog Integrated Circuits and Signal Processing
  • Year:
  • 2012

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Abstract

This paper describes the theory of operation, mathematical analysis, modeling and circuit design of the true piecewise approximation logarithmic amplifiers. These logarithmic amplifiers can be realized by the series linear limit and parallel summation methods. Both of these methods are discussed in this paper and their transfer functions are extracted. In addition, making use of the proposed formulas, a new mathematical approach is proposed for improving the characteristics of the parallel summation method. All of the presented methods are modeled in Simulink. Moreover, they are designed in a 0.13 μm CMOS technology and simulated by HSPICE. It is observed that analytical results comply with the simulation results. Considering the dynamic range, power, and area, the parallel summation method shows better performance than its series linear limit counterpart.