Design tradeoffs for sub-mW CMOS biomedical limiting amplifiers

Authors:
J. Ramos;J. L. Ausín;G. Torelli;J. F. Duque-Carrillo
Affiliations:
Department of Electrical and Electronic Engineering, University of Extremadura, Badajoz, Spain;Department of Electrical and Electronic Engineering, University of Extremadura, Badajoz, Spain;Dipartimento di Ingegneria Industriale e dell'Informazione, University of Pavia, Pavia, Italy;Department of Electrical and Electronic Engineering, University of Extremadura, Badajoz, Spain
Venue:
Microelectronics Journal
Year:
2013

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Design of Analog CMOS Integrated Circuits

Design of Analog CMOS Integrated Circuits
Analysis and design of the true piecewise approximation logarithmic amplifiers

Analog Integrated Circuits and Signal Processing

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Abstract

This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process spreads and devices mismatches was designed in 0.35@mm CMOS technology to operate over dc to 20MHz bandwidth and experimentally evaluated. The proposed limiting amplifier draws 280@mA from a 2-V supply and achieves a voltage gain of 72dB.