0.5 V CMOS inverter-based tunable transconductor

Authors:
S. Vlassis
Affiliations:
Electronics Laboratory, Department of Physics, University of Patras, Rio, Patras, Greece 26504
Venue:
Analog Integrated Circuits and Signal Processing
Year:
2012

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Abstract

A new technique for CMOS inverter-based tunable transconductors is proposed in this paper. The proposed technique employs the master---slave approach and offers large transconductance tuning range using a control current. The transconductor was designed using triple-well 0.13 μm CMOS process under the ultra low supply voltage of 0.5 V. The circuit features 37 dB open loop gain, CMRR = 31 dB at each output node, PSRR = 90 dB and GBW = 530 MHz for 120 μA current consumption.