CMOS: Circuit Design, Layout, and Simulation (IEEE Press Series on Microelectronic Systems)
CMOS: Circuit Design, Layout, and Simulation (IEEE Press Series on Microelectronic Systems)
A low power tunable Gm---C filter based on double CMOS inverters in 0.35 μm
Analog Integrated Circuits and Signal Processing
0.5 V CMOS inverter-based tunable transconductor
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing
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A new operational transconductance amplifier (OTA) builds with CMOS inverters only is proposed in this paper. Simulations with typical BSIM3V3 parameters of a 0.35 μm CMOS process have shown a 3.56 GHz gain-bandwidth product under 2.5 V supply voltage. The corresponding total harmonic distortion is equal to 0.46% for 2 V peak---peak differential output voltage. At the same supply voltage, the circuit can provided at each output a voltage swing of 2.25 V peak---peak. From VDD = 2 V to VDD = 2.5 V the differential transconductance varies from 72 to 108.4 μ驴驴1. The corresponding common mode rejection ratio and the total power consumption are always lower than 驴31 dBc and 800 μW, respectively. Typical application of a biquad filter is proposed to illustrate the circuit capabilities.