Low-voltage memories for power-aware systems
Proceedings of the 2002 international symposium on Low power electronics and design
A Feasibility Study of Subthreshold SRAM Across Technology Generations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Energy-efficient subthreshold processor design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Sub-threshold circuit design is a prevalent selection for ultra-low power (ULP) systems. Static random access memory (SRAM) is an important component in these systems therefore ultra-low power SRAM has become popular. Operation of standard 6T SRAM at sub or near-threshold voltages is unfeasible, predominantly due to degraded static noise margin (SNM) and fluctuations in MOSFET currents because of process variations at ultra-low voltages. Hence, many researchers have deliberated divergent configuration SRAMs for sub-threshold operations having 8T, 9T and 10T bit-cells for enhanced stability. Sub-threshold SRAMs have many important design issues such as cell stability, leakage current and area. In this paper, we give a deep insight of sub-threshold SRAM cell design issues and discuss several important circuit techniques. We emphasize on SRAM cell stability during read operation, develop read port circuits to design an ultra-low power sub-threshold SRAM cell. We propose 9T bit-cell that effectively improve read margin, thereby achieving high cell stability at 45nm technology node. The proposed design shows the full functionality of SRAM cell at a voltage down to around 500-200mV. The proposed design employs standard circuit techniques to improve read margins, as well as to allow a large number of bit-cells on single bit-line.