LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
Modeling Reactive Systems with Statecharts: The Statemate Approach
Modeling Reactive Systems with Statecharts: The Statemate Approach
Theory of Modeling and Simulation
Theory of Modeling and Simulation
GDEVS: A Generalized Discrete Event Specification for Accurate Modeling of Dynamic Systems
ISADS '01 Proceedings of the Fifth International Symposium on Autonomous Decentralized Systems
UML 2 Toolkit
Inference of Message Sequence Charts
IEEE Transactions on Software Engineering
Monitoring and control in scenario-based requirements analysis
Proceedings of the 27th international conference on Software engineering
A comparative survey of scenario-based to state-based model synthesis approaches
Proceedings of the 2006 international workshop on Scenarios and state machines: models, algorithms, and tools
Scenarios, goals, and state machines: a win-win partnership for model synthesis
Proceedings of the 14th ACM SIGSOFT international symposium on Foundations of software engineering
Detecting Implied Scenarios from Execution Traces
WCRE '07 Proceedings of the 14th Working Conference on Reverse Engineering
Synthesizing scenarios to DEVS models
Proceedings of the 2008 Spring simulation multiconference
Verification and validation of simulation models
Proceedings of the 40th Conference on Winter Simulation
Detecting implied scenarios analyzing non-local branching choices
FASE'03 Proceedings of the 6th international conference on Fundamental approaches to software engineering
Synthesis revisited: generating statechart models from scenario-based requirements
Formal Methods in Software and Systems Modeling
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The scenarios and the state-based models are two successful tools to describe the behavior of an interaction-based system. Scenarios are powerful to model and analyze software systems. However, since they do not provide a complete description of the system, but just some possible execution paths, they are usually integrated with state-based models. Working in parallel with the requirements of a system expressed in the form of scenarios, and its specification provided by the state-based models improves the level and quality of specification. Several works have been done to explain how to automatically generate state machines from scenarios requirement models. These works lead automatically to maintain consistency between scenarios and state machines. In this paper we propose an approach for detecting implied scenarios based on synthesized Discrete EVent System DEVS models from scenarios. This approach identifies unexpected state transition paths from atomic and coupled DEVS models generated. By detecting implied scenarios, analysts or users can further refine their requirements before implementation. The specification and the behavior of the final system are validated through simulation.