LSCs: Breathing Life into Message Sequence Charts
Formal Methods in System Design
Theory of Modeling and Simulation
Theory of Modeling and Simulation
Simulation and verification II: from timed automata to DEVS models
Proceedings of the 35th conference on Winter simulation: driving innovation
A comparative survey of scenario-based to state-based model synthesis approaches
Proceedings of the 2006 international workshop on Scenarios and state machines: models, algorithms, and tools
MSC scenarios analysis via simulation and formal verification techniques
GCMS '09 Proceedings of the 2009 Grand Challenges in Modeling & Simulation Conference
Validating interaction-based systems behavior via simulation and detecting implied scenarios
SCSC '09 Proceedings of the 2009 Summer Computer Simulation Conference
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Scenarios are widely used in the requirement phase of system development for the behavior specification of reactive systems. They provide a graphical way to capture sample behaviors corresponding to typical use cases. Transforming scenario-based to state-based specification brings the gap between a set of partial system behaviors and a full and global behavioral specification that constitutes the final objective of behavioral modeling. This paper explores some ways to synthesize an approximation of the global behavioral specification from scenarios, expressing the target specification with the DEVS formalism, that is a wider formalism than state-based formalisms associated to an unambiguous operational semantics. Then, the obtained DEVS specification can be simulated to be validated by end-users.