Communication systems engineering
Communication systems engineering
High-Speed Low-Current Duobinary Signaling Over Active Terminated Chip-to-Chip Interconnect
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
A comparative study of 20-Gb/s NRZ and duobinary signaling using statistical analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Increasing data rates over electrical channels with significant frequency-dependent loss is difficult due to excessive inter-symbol interference (ISI). In order to achieve sufficient link margins at high rates, I/O system designers implement equalization in the transmitters and are motivated to consider more spectrally-efficient modulation formats relative to the common PAM-2 scheme, such as PAM-4 and duobinary. This paper reviews when to consider PAM-4 and duobinary formats, as the modulation scheme which yields the highest system margins at a given data rate is a function of the channel loss profile, and presents a 20Gb/s triple-mode transmitter capable of efficiently implementing these three modulation schemes and three-tap feed-forward equalization. A statistical link modeling tool, which models ISI, crosstalk, random noise, and timing jitter, is developed to compare the three common modulation formats operating on electrical backplane channel models. In order to improve duobinary modulation efficiency, a low-power quarter-rate duobinary precoder circuit is proposed which provides significant timing margin improvement relative to full-rate precoders. Simulation results of the proposed transmitter in a 90nm CMOS technology compare operation with the different modulation schemes over three backplane channels with different loss profiles.