Algorithms and DSP implementation of H.264/AVC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
ASIP Approach for Implementation of H.264/AVC
Journal of Signal Processing Systems
Deblocking of block-transform compressed images using weighted sums of symmetrically aligned pixels
IEEE Transactions on Image Processing
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
Iterative procedures for reduction of blocking effects in transform image coding
IEEE Transactions on Circuits and Systems for Video Technology
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Complementary units in the form encoders and decoders are generally involved in video compression standards. Both the encoder and the decoder integrate an adaptive deblocking filter, which is very beneficial in preserving and enhancing the video quality. Deblocking filters are extremely popular in improving the visual quality of decoded frames in the H.264/AVC video coding standard. The prime goal of the current paper is to efficiently implement a H.264/AVC adaptive deblocking filter using the Texas Instruments DM6437EVM DSP processor. The adopted approach requires an initial identification of the portions of the algorithm wherein parallel processing can be exploited. The functions are then re-written and the instructions rearranged using the features of the targeted hardware architecture. The adaptive deblocking algorithm was optimised and ported to a DM6437EVM DSP platform. A quick comparison shows that the optimised code is a 32 % better, in terms of speed, than the non-optimised code.