A Heuristically-Aided Algorithm for Mutual Exclusion in Distributed Systems
IEEE Transactions on Computers
Partial orders for parallel debugging
PADD '88 Proceedings of the 1988 ACM SIGPLAN and SIGOPS workshop on Parallel and distributed debugging
ACM Transactions on Programming Languages and Systems (TOPLAS)
Journal of Algorithms
A stream compiler for communication-exposed architectures
Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
StreamIt: A Language for Streaming Applications
CC '02 Proceedings of the 11th International Conference on Compiler Construction
An Offline Algorithm for Dimension-Bound Analysis
ICPP '99 Proceedings of the 1999 International Conference on Parallel Processing
Scheduling Dynamic Dataflow Graphs with Bounded Memory
Scheduling Dynamic Dataflow Graphs with Bounded Memory
Brook for GPUs: stream computing on graphics hardware
ACM SIGGRAPH 2004 Papers
Language and compiler design for streaming applications
International Journal of Parallel Programming - Special issue: The next generation software program
Detection of Mutual Inconsistency in Distributed Systems
IEEE Transactions on Software Engineering
Distributed Computing: Principles, Algorithms, and Systems
Distributed Computing: Principles, Algorithms, and Systems
ΣC: a programming model and language for embedded manycores
ICA3PP'11 Proceedings of the 11th international conference on Algorithms and architectures for parallel processing - Volume Part I
IEEE Transactions on Signal Processing
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The ever-growing number of cores in Chip Multi-Processors (CMP) brings a renewed interest in stream programming to solve the programmability issues raised by massively parallel architectures. Stream programming languages are flourishing (StreaMIT, Brook, ∑C, etc.). Nonetheless, their execution support have not yet received enough attention, in particular regarding the new generation of many-cores. In embedded software, a lightweight solution can be implemented as a specialized library, but a dedicated micro-kernel offers a more flexible solution. We propose to explore the latter way with a Logical Vector Time based execution model, for CMP architectures with on-chip shared memory.