Optimal depth buffer for low-cost graphics hardware
HWWS '99 Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware
Hardware accelerated ambient occlusion techniques on GPUs
Proceedings of the 2007 symposium on Interactive 3D graphics and games
ACM SIGGRAPH 2007 courses
Minimum triangle separation for correct z-buffer occlusion
GH '06 Proceedings of the 21st ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware
ACM SIGGRAPH 2008 Games
Multi-layer dual-resolution screen-space ambient occlusion
SIGGRAPH 2009: Talks
Volumetric Ambient Occlusion for Real-Time Rendering and Games
IEEE Computer Graphics and Applications
Proceedings of the 2010 ACM SIGGRAPH symposium on Interactive 3D Graphics and Games
The alchemy screen-space ambient obscurance algorithm
Proceedings of the ACM SIGGRAPH Symposium on High Performance Graphics
Efficient screen-space approach to high-quality multiscale ambient occlusion
The Visual Computer: International Journal of Computer Graphics
Multi-view ambient occlusion with importance sampling
Proceedings of the ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games
Screen-space far-field ambient obscurance
Proceedings of the 5th High-Performance Graphics Conference
Dual space directional occlusion
The Visual Computer: International Journal of Computer Graphics
EGSR '13 Proceedings of the Eurographics Symposium on Rendering
| Hi-index | 0.00 |
This paper presents a set of architecture-aware performance and integration improvements for a recent screenspace ambient obscurance algorithm. These improvements collectively produce a 7 x performance increase at 2560 x1600, generalize the algorithm to both forward and deferred renderers, and eliminate the radius- and scene-dependence of the previous algorithm to provide a hard real-time guarantee of fixed execution time. The optimizations build on three strategies: pre-filter the depth buffer to maximize memory hierarchy efficiency; reduce total bandwidth by carefully reconstructing positions and normals at high precision from a depth buffer; and exploit low-level intra- and inter-thread techniques for parallel, floating-point architectures.