Space/time trade-offs in hash coding with allowable errors
Communications of the ACM
CoNEXT '06 Proceedings of the 2006 ACM CoNEXT conference
Towards a new generation of information-oriented internetworking architectures
CoNEXT '08 Proceedings of the 2008 ACM CoNEXT Conference
LIPSIN: line speed publish/subscribe inter-networking
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
Arguments for an information-centric internetworking architecture
ACM SIGCOMM Computer Communication Review
On name-based inter-domain routing
Computer Networks: The International Journal of Computer and Telecommunications Networking
Optimized hash for network path encoding with minimized false positives
Computer Networks: The International Journal of Computer and Telecommunications Networking
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This paper presents the design of a hardware accelerated forwarding architecture for processing packets that are labelled with a Bloom Filter (BF)-based header. The architecture consists of a conventional broadcast-and-select all-optical switching fabric, composed of Semiconductor Optical Amplifiers (SOAs), and a hardware-based Serial Processing Unit (SPU) that uses an on-the-fly processing mechanism to forward optical packets. The proposed SPU avoids the use of memory units and uses a small number of logic gates that facilitate a straightforward all-optical implementation using photonic logic gates. The SPU also supports flexible wavelength multicasting by allowing each incoming wavelength to be forwarded to any number of output ports. Contention resolution is provided by the introduction of an Optical Delay Line (ODL) that provides a single-packet optical buffer if the output channel is occupied.