Data Converters
Design of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing
Proceedings of the Conference on Design, Automation and Test in Europe
Operational Amplifiers: Theory and Design
Operational Amplifiers: Theory and Design
Focal-plane-arrays and CMOS readout techniques of infrared imaging systems
IEEE Transactions on Circuits and Systems for Video Technology
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This paper presents a low-noise and high dynamic-range CMOS readout-IC (ROIC) for a 64 脳 64 array of opto-electrical sensors. The readout chain comprises a pixel preamplifier array, correlated-double-sampling based switched-capacitor gain blocks, class-AB output buffer for driving off-chip loads and a 12-bit pipeline ADC for on-chip digitization. The pixel preamplifiers array, occupying an area of 30 μm 脳 30 μm per pixel, can either be hybridized to a separate IR or UV sensor or can be used as monolithic visible-light active CMOS pixel-array after exposing (by etching the pad) the embedded photodiode under the bonding pads. The ROIC is designed and fabricated in 0.25 μm 1P/5 M CMOS technology with 5 mm 脳 5 mm of total dimensions. The integrated readout chain, in integrate-then-read mode, demonstrates a dynamic range of 72 dB for electrically emulated sensor currents from 25 pA to 100 nA. It can support a frame rate of 700 fps, with single fully-differential analog as well as 12-bit digital output, at 10 MHz while consuming 17 mW with on-chip biases.