Laplace transformation on the FT64 stream processor

Authors:
Yu Deng;Xuejun Yang;Xiaobo Yan;Kun Zeng
Affiliations:
PDL, School of Computer, National University of Defense Technology, Changsha, Hunan province, China;PDL, School of Computer, National University of Defense Technology, Changsha, Hunan province, China;PDL, School of Computer, National University of Defense Technology, Changsha, Hunan province, China;PDL, School of Computer, National University of Defense Technology, Changsha, Hunan province, China
Venue:
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2007

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Abstract

The stream architecture is one of the emerging architectures that address the memory-wall problem of modern processors. While it is successful in the domain of multimedia, its efficiency to scientific applications is increasingly concerned. This paper implements a stream program for Laplace transformation and evaluates its performance on the FT64 stream processor, which is the first implementation of a 64-bit stream processor for scientific computing. The stream program is optimized against the memory hierarchy of FT64 to minimize the expensive off-chip memory transfers. The preliminary results show that FT64 is more efficient than the traditional cache-based processor (Itanium2) for Laplace transformation.