A bypass mechanism to enhance branch predictor for SMT processors

Authors:
Yongfeng Pan;Xiaoya Fan;Liqiang He;Deli Wang
Affiliations:
Department of Computer Sciences, Northwestern Polytechnical University, China;Department of Computer Sciences, Northwestern Polytechnical University, China;Department of Computer Sciences, University of Cyprus, Cyprus;Department of Computer Sciences, Northwestern Polytechnical University, China
Venue:
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2007

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Abstract

Unlike traditional superscalar processors, Simultaneous Multithreaded processors can explore both instruction level parallelism and thread level parallelism at the same time. With a same fetch width, SMT does not fetch instructions from a single thread as deeply as in traditional superscalar processors. Meanwhile, all the instructions from different threads share the same Function Units in SMT. All the characteristics make it possible to enhance the performance of SMT by reducing the branch mis-predictions. Based on the fact that about 15% of branch instructions directions can be definitely known at predicting cycle, a simple and effective bypass mechanism is proposed. This scheme doesn't depend on any existing branch predictors, and it can be used as an effective enhancement to any one of them. Execution-driven simulation results show that the branch miss prediction rates of our predictor decrease by more than 15% on average compared to a simple base line (g-share) predictor and improve the instruction throughput by about 2.5%.