Hardware implementation of common protocol interface for a network-based multiprocessor

  • Authors:

  • Arata Shinozaki;Mitsunori Kubo;Takayuki Nakatomi;Baoliu Ye;Minyi Guo

  • Affiliations:

  • Future Creation Lab., Olympus Corp., Shinjuku-ku, Tokyo, Japan;Future Creation Lab., Olympus Corp., Shinjuku-ku, Tokyo, Japan;Future Creation Lab., Olympus Corp., Shinjuku-ku, Tokyo, Japan;School of Computer Science and Eng., Aizu Univ., Aizu-Wakamatsu, Japan;School of Computer Science and Eng., Aizu Univ., Aizu-Wakamatsu, Japan

  • Venue:
  • ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
  • Year:
  • 2007

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Abstract

Our research project "UMP-PJ" has suggested the UMP Network Architecture for the next-generation computing infrastructure, in which each network node is coordinated each other. We have conducted the research on the basic architecture of the UMP Network, and shown its usefulness in the last papers. We defined a Processing Element (PE) comprised of PE Wrapper and PE Core. PE Wrapper is a common network interface of network node for UMP Network, and PE Core is an appreciation-specific function module. This paper evaluates the hardware implementation of PE. Especially, PE Wrapper is the key to satisfy the scalability and flexibility of UMP Network Architecture. The experimental model processed JPEG encoding application successfully with a PE implemented with an FPGA board on PC in conjunction with other software PEs. Experimental results demonstrate that no system bottleneck and redundant processing are caused by PE Wrapper implemented with hardware. This implies UMP Network Architecture is suitable for hardware implementation.