MIPS RISC architectures
Shade: a fast instruction-set simulator for execution profiling
SIGMETRICS '94 Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems
Parallel programming with MPI
System Design with SystemC
Complete Computer System Simulation: The SimOS Approach
IEEE Parallel & Distributed Technology: Systems & Technology
MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors
MASCOTS '94 Proceedings of the Second International Workshop on Modeling, Analysis, and Simulation On Computer and Telecommunication Systems
Reference Filtering for Distributed Simulation of Shared Memory Multiprocessors
SS '01 Proceedings of the 34th Annual Simulation Symposium (SS01)
Design of a simulator for mesh-based reconfigurable architectures
NPC'07 Proceedings of the 2007 IFIP international conference on Network and parallel computing
A scalable multiprocessor architecture for pervasive computing
GPC'11 Proceedings of the 6th international conference on Advances in grid and pervasive computing
Hardware implementation of common protocol interface for a network-based multiprocessor
ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
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In the ubiquitous era, it is necessary to research on the architectures of multiprocessor system with high performance and low power consumption. A processor simulator developed in high level language is useful because of its easily changeable system architecture which includes application specific instruction sets and functions. However, there is a problem in processing speed that both PCs and workstations provide insufficient performance for the simulation of a multiprocessor system. In this research, a simulator for a multiprocessor system based on the multi-way cluster was developed. In the developed simulator system, one processor model consists of an instruction set simulator (ISS) process and several inter-processor communication processes. In order to get the maximization of the simulation performance, each processor model is assigned to the specific CPU on the multi-way cluster. Also, each inter-processor communication process is implemented using MPI library, which can minimize the CPU resource usage in a communication waiting state. The evaluation results of the processing and communication performance using a distributed application program such as JPEG encoding show that each ISS process in the developed simulator system consumes approximately 100% CPU resources for keeping enough inter-processor communication performance. This result means that the performance increases in proportion to the number of integrated CPUs on the cluster.