Parallel lattice basis reduction
ISSAC '92 Papers from the international symposium on Symbolic and algebraic computation
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Mathematical Programming: Series A and B
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Journal of the ACM (JACM)
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CRYPTO '09 Proceedings of the 29th Annual International Cryptology Conference on Advances in Cryptology
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SIAM Journal on Computing
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LATINCRYPT'10 Proceedings of the First international conference on Progress in cryptology: cryptology and information security in Latin America
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IEEE Transactions on Information Theory
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Recent lattice enumeration GPU implementations are very useful to find shortest vectors within a given lattice but are also highly dependent on a lattice basis reduction that still runs on a CPU. Therefore we present an implementation of a full lattice basis reduction that makes exclusive use of GPUs to close this gap. Hence, we show that GPUs are, as well, suited to apply lattice basis reduction algorithms that were merely of theoretical interest so far due to their enormous computational effort. We modified and optimized these algorithms to fit the architecture of graphics cards, in particular we focused on Givens Rotations and the All-swap reduction method. Eventually, our GPU implementation achieved a significant speed-up for given lattice challenges compared to the NTL implementation running on an CPU of about 18, providing at least the same reduction quality.