The Compilation of Regular Expressions into Integrated Circuits
Journal of the ACM (JACM)
Elements of the Theory of Computation
Elements of the Theory of Computation
Assisting Network Intrusion Detection with Reconfigurable Hardware
FCCM '02 Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Scalable Pattern Matching for High Speed Networks
FCCM '04 Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Fast Regular Expression Matching Using FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A Scalable Architecture For High-Throughput Regular-Expression Pattern Matching
Proceedings of the 33rd annual international symposium on Computer Architecture
Optimization of pattern matching circuits for regular expression on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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To investigating high throughput pattern matching of regular expressions, This paper present a novel NFA-based architecture. In this paper, two theorems were proved and were used to prove the correctness of the algorithm. Our approach was based on three basic module to construct NFA which easily were reused in a FPGA or ASIC. Our approach is able to process many symbols per one clock cycle, and to run at high frequency. Due to FPGA constraints, the throughput of our approach achieved 512Gbps. The latency of our approach is lower than 2ns.