Modeling and analysis of CPU usage in safety-critical embedded systems to support stress testing

  • Authors:

  • Shiva Nejati;Stefano Di Alesio;Mehrdad Sabetzadeh;Lionel Briand

  • Affiliations:

  • SnT Center, University of Luxembourg, Luxembourg;SnT Center, University of Luxembourg, Luxembourg, Simula Research Laboratory, Certus Software V&V Center, Norway;SnT Center, University of Luxembourg, Luxembourg;SnT Center, University of Luxembourg, Luxembourg, Simula Research Laboratory, Certus Software V&V Center, Norway

  • Venue:
  • MODELS'12 Proceedings of the 15th international conference on Model Driven Engineering Languages and Systems
  • Year:
  • 2012

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Abstract

Software safety certification needs to address non-functional constraints with safety implications, e.g., deadlines, throughput, and CPU and memory usage. In this paper, we focus on CPU usage constraints and provide a framework to support the derivation of test cases that maximize the chances of violating CPU usage requirements. We develop a conceptual model specifying the generic abstractions required for analyzing CPU usage and provide a mapping between these abstractions and UML/MARTE. Using this model, we formulate CPU usage analysis as a constraint optimization problem and provide an implementation of our approach in a state-of-the-art optimization tool. We report an application of our approach to a case study from the maritime and energy domain. Through this case study, we argue that our approach (1) can be applied with a practically reasonable overhead in an industrial setting, and (2) is effective for identifying test cases that maximize CPU usage.