Towards one cycle per bit asymmetric encryption: code-based cryptography on reconfigurable hardware

  • Authors:
  • Stefan Heyse;Tim Güneysu

  • Affiliations:
  • Horst Görtz Institute for IT-Security, Ruhr-Universität Bochum, Bochum, Germany;Horst Görtz Institute for IT-Security, Ruhr-Universität Bochum, Bochum, Germany

  • Venue:
  • CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
  • Year:
  • 2012

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Abstract

Most advanced security systems rely on public-key schemes based either on the factorization or the discrete logarithm problem. Since both problems are known to be closely related, a major breakthrough in cryptanalysis tackling one of those problems could render a large set of cryptosystems completely useless. Code-based public-key schemes are based on the alternative security assumption that decoding generic linear binary codes is NP-complete. In the past, most researchers focused on the McEliece cryptosystem, neglecting the fact that the scheme by Niederreiter has some important advantages. Smaller keys, more practical plain and ciphertext sizes and less computations. In this work we describe a novel FPGA implementation of the Niederreiter scheme, showing that its advantages can result a very efficient design for an asymmetric cryptosystem that can encrypt more than 1.5 million plaintexts per seconds on a Xilinx Virtex-6 FPGA, outperforming all other popular public key cryptosystems by far.