Embedded systems for IT security applications: properties and design considerations
Proceedings of the 2nd international conference on Security of information and networks
A timing attack against patterson algorithm in the McEliece PKC
ICISC'09 Proceedings of the 12th international conference on Information security and cryptology
A novel cryptoprocessor architecture for chained Merkle signature scheme
Microprocessors & Microsystems
An FPGA accelerator for hash tree generation in the merkle signature scheme
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Practical power analysis attacks on software implementations of mceliece
PQCrypto'10 Proceedings of the Third international conference on Post-Quantum Cryptography
ISC'12 Proceedings of the 15th international conference on Information Security
Towards one cycle per bit asymmetric encryption: code-based cryptography on reconfigurable hardware
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Smaller keys for code-based cryptography: QC-MDPC mceliece implementations on embedded devices
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
Hi-index | 0.00 |
McEliece scheme represents a code-based public-key cryptosystem. So far, this cryptosystem was not employed because of efficiency questions regarding performance and communication overhead.This paper presents a novel processor architecture as a high-performance platform to execute key generation, encryption and decryption according to this cryptosystem. A prototype of this processor is realized on Virtex-5 FPGA and tested via a software API. A comparison with a similar software solution highlights the performance advantage of the proposed hardware solution.