A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n)
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Dependability-Driven System-Level Design Approach for Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms
ASAP '09 Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors
High-Performance Rekeying Processor Architecture for Group Key Management
IEEE Transactions on Computers
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Embedded systems aimed for applications in the IT security domain are characterized by specific needs in terms of computing power. The high computational loads stem both from algorithms, which have to address different symmetric and especially asymmetric encryption schemes such as AES, RSA, ECC and PBC, and from associated key size values ranging from 100's to several 1000's bits. This presentation details specific architectural considerations of reconfigurable System-on-Chip implementations aimed to deal with high computational loads. Multiple data paths with pipelining, distributed memory blocks, and multiple processor/coprocessor schemes are presented and demonstrated for several application examples including quantum computing resistant encryption. The design flow for such specific architectures will be addressed by means of a dedicated high-level synthesis tool, which is based on genetic algorithms for the solution of the underlying allocation and scheduling problem.